How the below verilog code run when it find positive edge of clock?

How the below verilog code run when it find positive edge of clock?
rd=1; case1=2 ; i=2; n1=23; always @(posedge clka) begin counter=counter+1; if (rd==1) begin #5 window[i]<=douta; ~~~~~~~~~~~ Statement1 case(i) case1: addra=n1; case2: addra= n2; endcase #5 addra<=addra+1; ~~~~~~~~~~~Statement2 #5 i<=i+1; end end
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What you are running into is confusion about blocking vs non-blocking how much is a smog check assignment. This is a nice example as to why it is called non-blocking assignment. When you hit the line #5 window[i]<=douta; , the simulator will wait 5 time units, how much is a smog check then schedule window[i] to take on the value of douta at the end of the current time step. Because you used the non-blocking assignment operator, how much is a smog check the execution of the always block continues to the next statements, which is the case statement. Since the assigns here are blocking assignments, they are executed immediately. Then, the #5 is hit (after the case), so the scheduler schedules the next execution for 5 time units in the future. Then it moves on to anything how much is a smog check else it needs to do. Finally, it comes back (still within time step X+5) and completes how much is a smog check all the non-blocking assignments (like window[i]<=douta ). Thats why you are seeing what looks like non-inorder execution of your always block.
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